News Coverage

(July 17, 2023) - EETimes - Quadric’s Chimera family of general-purpose neural processor cores combines a neural processing accelerator with the full C++ programmability of a digital-signal processor.

(July 5, 2023) SemiWiki - More generally, new architectures in AI stimulate a flood of new techniques, already apparent in many ViT papers over just the last couple of years. Which means that accelerators will need to be friendly to both traditional and transformer models. That bodes well for Quadric, whose Chimera General-Purpose NPU (GPNPU) processors are designed to be a single processor solution for all AI/ML compute, handling image pre-processing, inference, and post-processing all in the same core. Since all compute is handled in a single core with a shared memory hierarchy, no data movement is needed between compute nodes for different types of ML operators.

(June 20, 2023) SemiEngineering - Vision Transformers are not CNNs and many of the assumptions made by the designers of first-generation Neural Processing Unit (NPU) and AI hardware accelerators found in today’s SoCs do not translate well to this new class of models.

(June 18, 2023) SemiEngineering - In any kind of edge inference product...there will basically be three types of functional software, largely coming from three different types of developers — data scientists, embedded CPU developers, and DSP developers....How to program DSPs, CPUs and NPUs will vary depending on applications, use cases, system architectures, and environments. That will determine how to optimization the code to achieve the best performance for a particular application or use model.

(May 22, 2023) SemiWiki - The mainstream architecture for the intelligent edge combines a neural net for inference, a DSP for vector processing and a CPU/cluster for scalar processing and control...The Quadric Chimera engine combines all three operation types in one processor with a unified instruction pipeline, starting with a common instruction fetch, then branching into a conventional ALU pipeline for scalar elements and a dataflow pipeline built on a 2D matrix of processing elements (PEs) and local registers for matrix/vector operations.

(May 25, 2023) SemiEngineering - “The core tenet of the IP industry is reuse. That means repeatedly delivering the same block over and over again, which means planning for a design element to be used in different system architectures, in different market segments, under different conditions," said Dhanendra Jani, VP Engineering, Quadric.

(May 16, 2023)  SemiEngineering - Quadric introduced the Quadric Developer Studio, an online collaborative development environment for Chimera general-purpose neural processing unit (GPNPU) processors. Quadric DevStudio speeds software development with the industry’s first integrated machine learning (ML) plus digital signal processing (DSP) development system.

(April 28, 2023) SemiWiki - Dan explores the unique and unified HW/SW architecture developed by Quadric with Nigel Drego. The benefits of a single architecture programmable approach to on-chip AI is explained, along with specific examples of how to adapt the system to various AI processing challenges.

(Apr 13, 2023) SemiEngineering - The bottom line – a hardwired accelerator optimized in 2017 for ResNet would be fundamentally broken – almost useless – in trying to run today’s SOTA ML model. History is bound to repeat.

(Mar 14 2023) SemiEngineering - AI inference benchmarks, such as MLPerf’s, do not represent all of the facets of AI compute relevant to application developers. Further, they distract SoC designers from optimizing performance for end-to-end AI applications that will enable them to capture the fast-growing AI hardware market. For the entire AI compute, there are at present no standardized benchmarks.