News Coverage

(August 23, 2023) The Ojo-Yoshida Report - Roddy sees Quadric’s strength in its ability to run different kernels doing different jobs – tasks classically thought of as DSP code, kernels for classic neural nets including one for a detector, another for an authenticator, and something in between doing CPU-like tasks – all on Quadric’s “single processor.” Roddy explained, “There’s no multiple engines inside the hood. There’s one actual processor, one execution pipeline, one code stream that all gets compiled together.”

(August 24, 2023) Semiconductor Engineering - What’s new today, in 2023, is that the rapid rush of machine learning inference is simultaneously disturbing nearly all types of subsystems. The known characteristics of proven building blocks that might have allowed a team to use heuristic approaches to size system resources — memory, bus bandwidth, I/O bandwidth, power management — are all disrupted.

(August 10, 2023) Semiconductor Engineering - While most fixed-function NN accelerators cannot run Vision Transformers at all, Quadric not only runs transformers, but is poised to continue to deliver large increases in performance – without hardware changes – as the CGC to LLVM compiler stack continues to mature and improve.

(July 20 2023) SemiEngineering - In today’s modern world of electronics, the headlong rush to build and deploy machine learning (ML) based artificial intelligence into devices and systems creates its own Mars – Venus clash of cultures.

(July 17, 2023) - EETimes - Quadric’s Chimera family of general-purpose neural processor cores combines a neural processing accelerator with the full C++ programmability of a digital-signal processor.

(July 5, 2023) SemiWiki - More generally, new architectures in AI stimulate a flood of new techniques, already apparent in many ViT papers over just the last couple of years. Which means that accelerators will need to be friendly to both traditional and transformer models. That bodes well for Quadric, whose Chimera General-Purpose NPU (GPNPU) processors are designed to be a single processor solution for all AI/ML compute, handling image pre-processing, inference, and post-processing all in the same core. Since all compute is handled in a single core with a shared memory hierarchy, no data movement is needed between compute nodes for different types of ML operators.

(June 20, 2023) SemiEngineering - Vision Transformers are not CNNs and many of the assumptions made by the designers of first-generation Neural Processing Unit (NPU) and AI hardware accelerators found in today’s SoCs do not translate well to this new class of models.

(June 18, 2023) SemiEngineering - In any kind of edge inference product...there will basically be three types of functional software, largely coming from three different types of developers — data scientists, embedded CPU developers, and DSP developers....How to program DSPs, CPUs and NPUs will vary depending on applications, use cases, system architectures, and environments. That will determine how to optimization the code to achieve the best performance for a particular application or use model.

(May 22, 2023) SemiWiki - The mainstream architecture for the intelligent edge combines a neural net for inference, a DSP for vector processing and a CPU/cluster for scalar processing and control...The Quadric Chimera engine combines all three operation types in one processor with a unified instruction pipeline, starting with a common instruction fetch, then branching into a conventional ALU pipeline for scalar elements and a dataflow pipeline built on a 2D matrix of processing elements (PEs) and local registers for matrix/vector operations.

(May 25, 2023) SemiEngineering - “The core tenet of the IP industry is reuse. That means repeatedly delivering the same block over and over again, which means planning for a design element to be used in different system architectures, in different market segments, under different conditions," said Dhanendra Jani, VP Engineering, Quadric.