News Coverage

So how does the algorithm porting team handle porting of Voxel Pooling onto an embedded NPU if the function is not represented in the graph interchange format supported by the NPU vendor’s graph compiler toolchain? With other NPUs, the team is stuck – there’s simply no way to get that important new function ported quickly to the NPU, and very likely it can never be ported. BEVdepth might simply not be able to run on the platform at all.

(March 6, 2025) Junko's Tech Probe - Japanese IC vendors lost their way by sticking too long to in-house fabs, insisting on home-grown MCUs and tool sets. But rapid advancements in AI could nudge Japan toward embracing "buy" over "make."

The autonomous driving sector has seen an influx of investment in the past year after nearly a decade in the doldrums. “We’ve been in this space about seven years now, and the last 12 months of activity dwarfs everything I’ve seen,” says Veerbhan Kheterpal, co-founder and CEO at Quadric, a startup developing processor architecture for the AI chips needed for self-driving cars.

(February 18, 2025) SemiWiki - 2024 was a year of tremendous momentum building for Quadric.  We introduced and began customer deliveries of the 2^nd generation of our Chimera GPNPU processor, which now scales to over 800 TOPs.  We also dramatically expanded the size of our model zoo (available in our online DevStudio at our quadric.io website) from only 20 models at the start of the year to over 200 by the close of 2024 thanks to the rapid maturation of our compiler stack.

(February 17, 2025) Semiconductor Engineering - The rapid emergence of Vision Language Models (VLMs) in the automotive/ADAS sector is one of those under-the-public-radar changes shaking up a different industry...Vision Language Models are multimodal AI systems built by combining a large language model (LLM) with a vision encoder, giving the LLM the ability to “see.”

(January 16, 2025) - Semiconductor Engineering - True, the idea of a partitioned (programmable core) + (MAC tensor engine) worked quite well in 2021 to run classic CNNs from the Resnet era (circa 2015-2017). But we have argued that modern CNNs and all new transformers are comprised of much more varied ML network operators – and far more complex, non-MAC functions – than the simple eight (8) operator Resnet-50 backbone of long ago.

(November 20, 2024) SemiWiki - Survival of the fittest is likely to play out even faster here than it did around a much earlier proliferation of CPU platforms. We still need competition between a few options, but the current Cambrian explosion of edge NPUs must come to an end fairly quickly, one way or another.

(November 18, 2024) Semiconductor Engineering - If you are comparing alternatives for an NPU selection, give special attention to clearly identifying how the NPU/GPNPU will be used in your target system, and make sure the NPU/GPNPU vendor is reporting the benchmarks in a way that matches your system needs. Many NPU vendors will only report their Batched results, because there can be substantial Inferences-Per-Second differences between Batch-1 and Batch N calculations.

(November 6, 2024) Electronics Weekly - The agreement means Denso will acquire the IP core license for Quadric’s Chimera general purpose NPU (GPNPU). Both companies will co-develop IP for an in-vehicle semiconductor for use in intelligent vehicle systems (ADAS and AD/self-driving) and inter-vehicle and cloud communications.

(October 17, 2024) Semiconductor Engineering - Just as the children’s Goldilocks fable always presented a “just right” alternative, the At-Memory compute architecture is the solution that is Just Right for edge and device SoCs....The best alternative for SoC designers is a solution that both take advantage of small local SRAMs – preferably distributed in large number among an array of compute elements – as well as intelligently scheduled data movement between those SRAMs and the off-chip storage of DDR memory in a way that minimizes system power consumption and minimizes data access latency.