News Coverage

In Memory, At Memory, Near Memory: What Would Goldilocks Choose?

(October 17, 2024) Semiconductor Engineering - Just as the children’s Goldilocks fable always presented a “just right” alternative, the At-Memory compute architecture is the solution that is Just Right for edge and device SoCs....The best alternative for SoC designers is a solution that both take advantage of small local SRAMs – preferably distributed in large number among an array of compute elements – as well as intelligently scheduled data movement between those SRAMs and the off-chip storage of DDR memory in a way that minimizes system power consumption and minimizes data access latency.

Mass Customization For AI Inference

(October 17, 2024) Semiconductor Engineering - "It is simply infeasible to build hard-wired logic to accelerate such a wide variety of networks comprised of hundreds of different variants of AI graph operators. SoC architects as a result are searching for more fully programmable solutions, and most internal teams are looking to outside third-party IP vendors that can provide the more robust compiler toolsets needed to rapidly compile new networks, rather than the previous labor-intensive method of hand-porting ML graphs."

Can You Rely Upon Your NPU Vendor To Be Your Customers’ Data Science Team?

(September 12, 2024) Semiconductor Engineering - The biggest mistake a chip design team can make in evaluating AI acceleration options for a new SoC is to rely entirely upon spreadsheets of performance numbers from the NPU vendor without going through the exercise of porting one or more new machine learning networks themselves using the vendor toolsets.

A New Class of Accelerator Debuts

(July 22, 2024) SemiWiki - Steve Roddy (VP Marketing for Quadric) tells me that in a virtual benchmark against a mainstream competitor, Quadric’s QC-Ultra IP delivered 2X more inferences/second/TOPs for a lower off-chip DDR bandwidth and at less than half the cycles/second of the competing solution. Quadric are now offering 3 platforms for the mainstream NPU market segment: QC Nano at 1-7 TOPs, QC Perform at 4-28 TOPs, and QC Ultra at 16-128 TOPs. That high end is already good enough to meet AI PC needs. Automotive users want more, especially for SAE-3 to SAE-5 applications. For this segment Quadric is targeting their QC-Multicore solution at up to 864 TOPs.

ConvNext Runs 28X Faster Than Fallback

(July 22, 2024) Semiconductor Engineering - Perhaps more impressive than our ability to support ConvNext – at a high 28 FPS frame rate – is the startling increase in the sheer number of working models that compile and run on the Chimera processor as our toolchain rapidly matures.

GPNPU has multi-core cluster options for +100TOPS

(July 16, 2024) Electronics Weekly - A component supplier … building a 3nm chiplet could deliver over 400TOPS of fully C++ programmable ML + DSP compute for software defined vehicle platforms for a die cost of well under $10.

KAN tackles AI power challenge

(July 8, 2024) EE News Europe - Quadric says its Chimera general purpose NPU is able to support KANs as well as the matrix-multiplication hardware needed to efficiently run conventional neural networks with a massively parallel array of general-purpose, C++ programmable ALUs capable of running any and all machine learning models.  Quadric’s Chimera QB16 processor, for instance, pairs 8192 MACs with a whopping 1024 full 32-bit fixed point ALUs, giving 32,768 bits of parallelism to run KAN networks.

Silicon 100: Startups Worth Watching in 2024

(July 8, 2024) - EETimes - Founded in 2016, Quadric is developing machine-learning software and platforms for autonomous vehicles and robots. Its Chimera GPNPU is a licensable processor IP core that scales from 1 to 16 TOPS in a single core and intermixes scalar, vector and matrix code. In a multicore configuration, Chimera scales to hundreds of TOPS.

KANs Explode!

(June 13, 2024) Semiconductor Engineering - In late April 2024, a novel AI research paper was published by researchers from MIT and CalTech proposing a fundamentally new approach to machine learning networks – the Kolmogorov Arnold Network – or KAN. In the six weeks since its publication, the AI research field is ablaze with excitement and speculation that KANs might be a breakthrough that dramatically alters the trajectory of AI models for the better – dramatically smaller model sizes delivering similar accuracy at orders of magnitude lower power consumption – both in training and inference.

The Fallacy of Operator Fallback and the Future of Machine Learning Accelerators

(May 30, 2024) SemiWiki - Managing the interplay between NPU, DSP, and CPU requires complex data transfers and synchronization, leading to increased system complexity and power consumption. Developers must contend with different programming environments and extensive porting efforts, making debugging across multiple cores even more challenging and reducing productivity.

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